1. Field of the Invention
The present invention relates to time to digital converting (TDC) circuits, and more particularly, to a time to digital converting (TDC) circuit utilizing delay circuits to generate periodic delay signals and a related method.
2. Description of the Prior Art
In general, a time to digital converting (TDC) circuit is utilized for measuring the delay level of a signal under test and transferring the abstract delay level into a physical delay amount provided by delay stage(s). That is, the time to digital converting circuit is capable of expressing the delay level of a signal under test by the number of delay stages. Taking a conventional time to digital converting circuit as an example, a first signal and a second signal are sent to a first delay circuit and a second delay circuit respectively. As a result, after a certain amount of time, the second signal will catch up with the first signal. When the two signals (i.e., the first signal and the second signal) are synchronized, the delay level of the first signal is derived by computing a total difference between the number of delay stages that the first signal has passed and the number of delay stages that the second signal has passed.
Ordinarily, a specified scheme different from the aforementioned one obtains a difference (i.e., ts−tf) between a certain delay stage (ts) having a larger delay amount and another delay stage (tf) having a smaller delay amount, and then represents a delay situation of the signal under test as N(ts−tf). Since the structure and operation of such a TDC circuit and the computing method thereof are well known to people skilled in this art, further description is omitted here for brevity.
The conventional TDC circuit and method thereof require the use of a complete delay circuit, however, resulting in a larger circuit area.